driver: clock_control: renesas_ra: Defining MSTP regs in devicetree #76820
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area: Devicetree Binding
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duynguyenxa
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@soburi , Seem good to me, we've checked this on RA8M1 hardware
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Allows MSTP register addresses to be changed in the device tree to support different configuration SoCs. Signed-off-by: TOKITA Hiroshi <[email protected]>
When omitting the clk_src definition in a child node of a pclkblock, it uses the source of the parent node. Signed-off-by: TOKITA Hiroshi <[email protected]>
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Add a definition for RA4, which was not included in zephyrproject-rtos#76820. Signed-off-by: TOKITA Hiroshi <[email protected]>
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Add a definition for RA4, which was not included in #76820. Signed-off-by: TOKITA Hiroshi <[email protected]>
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Add a definition for RA4, which was not included in zephyrproject-rtos#76820. (cherry picked from commit 1ffd746) Original-Signed-off-by: TOKITA Hiroshi <[email protected]> GitOrigin-RevId: 1ffd746 Cr-Build-Id: 8738238973287044049 Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8738238973287044049 Copybot-Job-Name: zephyr-main-copybot-downstream Change-Id: Idd2bc8bc5cb47ce9da5105edbd65f1bd4473b378 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5827586 Tested-by: ChromeOS Prod (Robot) <[email protected]> Tested-by: Ting Shen <[email protected]> Reviewed-by: Ting Shen <[email protected]> Commit-Queue: Ting Shen <[email protected]>
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Allows MSTP register addresses to be changed in the device tree
to support different configuration SoCs.
When omitting the clk_src definition in a child node of a pclkblock,
it uses the source of the parent node.
The impact is still limited, so we are currently correcting the names.Since I don't have an RA8M1 environment, I verified this PR with RA4M1 only.